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Intel Corporation Ethernet Controller 10-Gigabit X540-AT2

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The X540 is a derivative of the 82599, the Intel 10 GbE Network Interface Controller (NIC) targeted for blade servers.

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Compatible with

  • Citrix Hypervisor 8.0
  • XenServer 6.2
  • XenServer 6.5
  • XenServer 7.0
  • XenServer 7.1 LTSR
  • XenServer 7.2
  • XenServer 7.3
  • XenServer 7.4
  • XenServer 7.5
  • XenServer 7.6

Compatibility

  • Citrix Hypervisor (XenServer)

Product Details

The X540 is a derivative of the 82599, the Intel 10 GbE Network Interface Controller (NIC) targeted for blade servers. Many features of its predecessor remain intact;however, some have been removed or modified as well as new features introduced.

The X540 includes two integrated 10GBASE-T copper Physical Layer Transceivers (PHYs). A standard MDIO interface, accessible to software via MAC control registers, is used to configure and monitor each PHY operation.

The X540 also supports a single port configuration. The X540 is targeted for system configurations such as rack mounted or pedestal servers, where it can be used as an add-on NIC or LAN on Motherboard (LOM).

Features

General

  • Serial Flash interface
  • Configurable LED operation for software or customizing OEM LED displays
  • Device disable capability

Networking

  • 10 GbE/1 GbE/100 Mb/s copper PHYs integrated on-chip
  • Support for jumbo frames of up to 15.5 KB
  • Flow control support: send/receive pause frames and receive FIFO thresholds
  • Statistics for management and RMON
  • 802.1q VLAN support
  • TCP segmentation offload: up to 256 KB
  • IPv6 support for IP/TCP and IP/UDP receive checksum offload
  • Fragmented UDP checksum offload for packet reassembly
  • Message Signaled Interrupts (MSI)
  • Message Signaled Interrupts (MSI-X)
  • Interrupt throttling control to limit maximum interrupt rate and improve CPU usage
  • Flow Director (16 x 8 and 32 x 4)
  • 128 transmit queues
  • Receive packet split header
  • Receive header replication
  • Dynamic interrupt moderation
  • DCA support
  • TCP timer interrupts
  • No snoop
  • Relaxed ordering
  • Support for 64 virtual machines per port (64 VMs x 2 queues)
  • Support for Data Center Bridging (DCB);(802.1Qaz, 802.1Qbb, 802.1p)

Host Interface

  • PCIe base specification 2.1 (2.5GT/s or 5GT/s)
  • Bus width - x1, x2, x4, x8
  • 64-bit address support for systems using more than 4 GB of physical memory

MAC FUNCTIONS

  • Descriptor ring management hardware for transmit and receive
  • ACPI register set and power down functionality supporting D0 and D3 states
  • A mechanism for delaying/reducing transmit interrupts
  • Software-controlled global reset bit (resets everything except the configuration registers)
  • Four Software-Definable Pins (SDP) per port
  • Wake up
  • IPv6 wake-up filters
  • Configurable flexible filter (through NVM)
  • LAN function disable capability
  • Programmable memory transmit buffers (160 KB/port)
  • Default configuration by NVM for all LEDs for pre-driver functionality

Manageability

  • SR-IOV support
  • Eight VLAN L2 filters
  • 16 Flex L3 port filters
  • Four Flexible TCO filters
  • Four L3 address filters (IPv4)
  • Advanced pass through-compatible management packet transmit/receive support
  • SMBus interface to an external Manageability Controller (MC)
  • NC-SI interface to an external MC
  • Four L3 address filters (IPv6)
  • Four L2 address filters