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Intel Xeon E7-2800

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The Intel® Xeon® E7-2800 v2 processors are the next generation of 64-bit, multi-core enterprise processors built on 22-nanometer process technology.

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Compatible with

  • XenServer 6.0
  • XenServer 6.0.2
  • XenServer 6.1
  • XenServer 6.2
  • XenServer 6.5
  • XenServer 7.0

Compatibility

  • Citrix Hypervisor (XenServer)

Product Details

The Intel® Xeon® E7-2800 v2 processors are the next generation of 64-bit, multi-core enterprise processors built on 22-nanometer process technology. Based on the low-power/high performance Intel® Xeon® E7-2800 v2 processor microarchitecture, the processor is designed for a three-chip platform as opposed to the previous four-chip platform. The three-chip platform consists of a processor, memory buffer, and the Platform Controller Hub (PCH) and enables higher performance, easier validation, and improved x-y footprint. The Intel® Xeon® E7-2800 v2 processor is designed for enterprise workloads and maximum memory expendability.

The Intel® Xeon® E7-2800 v2 processor supports scalable server and HPC platforms of two or more processors, including “glueless” 8-way platforms. These processors feature per socket, four Intel® Scalable Memory Interconnect (Intel® SMI) Gen 2 memory links with speeds up to 2.67 GT/s, three Intel® QuickPath Interconnect (Intel® QPI) point-to-point links capable of up to 8.0 GT/s, up to 32 lanes of PCI Express 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express 2.0 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space. Included in this family of processors is integrated I/O (IIO) (such as PCI Express and DMI2) on a single silicon die. This single die solution is known as a monolithic processor.

Features

  • Each core supports two threads (Intel® Hyper-Threading Technology), up to 30 threads per socket
  • 46-bit physical addressing and 48-bit virtual addressing
  • A 32-KB instruction and 32-KB data first-level cache (L1) for each core
  • A 256-KB shared instruction/data mid-level (L2) cache for each core
  • Up to 37.5 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores
  • The Intel® Xeon® E7 v2 processor supports Directory Mode to reduce unnecessary Intel QuickPath Interconnect traffic by tracking cache lines present in remote sockets.